32-bit Superscalar RISC-V CPU

RISC-V Virtual Prototype

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, single…

A collection of links related to Linux kernel security and exploitation

RISC-V Assembly Programmer's Manual

Simodense: a RISC-V softcore for custom SIMD instructions

🐶 Automated code review tool integrated with any code analysis tools regardless of programming language

VeeR EL2 Core

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Bootlin embedded Linux and kernel training materials

Linux kernel crash utility

Complementary Concurrency Programs for course "Linux Kernel Internals"

PLCT实验室的公开演讲，或者决定公开的组内报告

List of Computer Science courses with video lectures.

A modeling library with virtual components for SystemC and TLM simulators

A little bit about a linux kernel

Papers from the computer science community to read and discuss.

This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.

🎓 Path to a free self-taught education in Computer Science!

📚 List of awesome university courses for learning Computer Science!

Must-have verilog systemverilog modules

Buildroot for T-HEAD XuanTie CPU Series

C/C++ hooks to integrate with pre-commit

linux内核学习资料：200+经典内核文章，100+内核论文，50+内核项目，500+内核面试题，80+内核视频

A basic working RISCV emulator written in C

Learning operating system development using Linux kernel and Raspberry Pi