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hwpe-stream Public
Forked from pulp-platform/hwpe-streamIPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
SystemVerilog Other UpdatedDec 6, 2024 -
hwpe-ctrl Public
Forked from pulp-platform/hwpe-ctrlIPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
SystemVerilog Other UpdatedDec 6, 2024 -
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hwpe-tb Public
Forked from pulp-platform/hwpe-tbTemplate testbench for HWPEs (using the hwpe-mac-engine as example)
Stata Other UpdatedOct 31, 2024 -
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xil_open_hw_23 Public
GenOv: Streamlining the Design and Optimization of Heterogeneous RISC-V-based FPGA Overlays
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hero Public
Forked from pulp-platform/heroHeterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software …
SystemVerilog Other UpdatedJun 21, 2023 -
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pulpissimo Public
Forked from pulp-platform/pulpissimoThis is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
C++ Other UpdatedDec 17, 2020 -
dummy_vip Public
Forked from pulp-training/dummy_vipFiles for the IP Integration Exercise
SystemVerilog UpdatedDec 17, 2020 -
pulpissimo-zcu102 Public
Forked from cmcmicrosystems/pulpissimo-zcu102Implementation of a 32-bit single core risc-v platfrom for Xilinx zcu102 board
SystemVerilog Other UpdatedNov 5, 2019