Sequential model-based optimization with a `scipy.optimize` interface

scikit-learn: machine learning in Python

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

My setup for writing LaTeX documents on Windows using WSL, VSCode & TeXLive

⭐ Vim for Visual Studio Code

An Open-Hardware CGRA for accelerated computation on the edge.

XLS: Accelerated HW Synthesis

EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)

Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at https://gitlab.com/buildroot.org/buildroot/. Do not open i…

Style guides for Google-originated open-source projects

Sphinx documentation with git submodules for common content

Simple Python style checker in one Python file

It's not just a linter that annoys you!

Data repository for my blog series on microprocessor trend data.

Open source AMD Xilinx Kria UltraScale+ SoM baseboard

VHDL for basic floating-point operations.

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

A Fast, Low-Overhead On-chip Network

AMD OpenNIC Project Overview

lowRISC Style Guides

Chisel: A Modern Hardware Design Language

The Task Parallel System Composer (TaPaSCo)

Code generation tool for control and status registers

AXI interface modules for Cocotb

Verilog AXI stream components for FPGA implementation

Template for the Read the Docs tutorial

Network on Chip Implementation written in SytemVerilog

A Chisel RTL generator for network-on-chip interconnects