SystemVerilog compiler and language services

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

draws an SVG schematic from a JSON netlist

🌊 Digital timing diagram rendering engine

Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

Build Customized FPGA Implementations for Vivado

The official GitHub mirror of the Chromium source

LevelDB is a fast key-value storage library written at Google that provides an ordered mapping from string keys to string values.

Icarus Verilog

Multi-platform nightly builds of open source digital design and verification tools

Place and route tool for FPGAs

Threshold logic operation within ABC

A logic synthesis tool

C++ logic network library

C++ logic network library

Showcase examples for EPFL logic synthesis libraries

KaHyPar (Karlsruhe Hypergraph Partitioning) is a multilevel hypergraph partitioning framework providing direct k-way and recursive bisection based partitioning algorithms that compute solutions of …

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Odin Programming Language

Abseil Common Libraries (C++)

KaHIP -- Karlsruhe HIGH Quality Partitioning.

METIS - Serial Graph Partitioning and Fill-reducing Matrix Ordering

ParMETIS - Parallel Graph Partitioning and Fill-reducing Matrix Ordering

记录 GacUI 开发10年来背后的故事，以及对架构设计的考量。

VHDL 2008/93/87 simulator

Torc: Tools for Open Reconfigurable Computing

The Z3 Theorem Prover

Dear ImGui: Bloat-free Graphical User interface for C++ with minimal dependencies