Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

A single channel morphology filter IP for ECG signals, etc.

APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS

Small footprint and configurable PCIe core

Tengine is a lite, high performance, modular inference engine for embedded device

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

stb single-file public domain libraries for C/C++

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP

Denoise,HDR,Isppipeline,Image-processing(图形处理),camera, Isp ,HDRplus

VHDL sources for a BT.656 to axi4-stream converter

Verilog module for flexible instantiation of ROM/RAM of arbitrary depth and bit width. Automatically reduce BRAM usage through depth division, bit width division, and bit width folding.

https://blog.csdn.net/ZhaoDongyu_AK47?spm=1011.2124.3001.5343

Must-have verilog systemverilog modules

基于verilog实现了ISP图像处理IP

基于verilog实现了ISP图像处理IP(Altera EP4CE6)

from https://gitee.com/wtzhu13/ISPAlgorithmStudy

http://openasic.org/

ZAP is a High Performance ARM(R) V5TE Compatible Superpipelined Processor with Caches, MMUs and TLBs that is capable of reaching 143MHz@Artix-7 FPGA. ZAP is Copyright (C) 2016-2022 Revanth Kamaraj.…

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

《智能计算系统 AI Computing Systems》习题答案、实验答案、课程笔记

PCIE 5.0 Graduation project (Verification Team) under supervision of Mentor Graphics

冈萨雷斯《数字图像处理》第三版-课后习题答案；《数字图像处理（matlab版）》-源代码及图片 DIP

该资源为作者在CSDN的撰写Python图像处理文章的支撑，主要是Python实现图像处理、图像识别、图像分类等算法代码实现，希望该资源对您有所帮助，一起加油。