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Commits on Oct 20, 2017

• [globalisel][tablegen] Fix small spelling nits. NFC

  Show description for d83b5d4
  dsandersllvm

  committed
  d83b5d4

• [Hexagon] Report error instead of crashing on wrong inline-asm constraints

  Show description for 736ecc1
  

  Krzysztof Parzyszek

  committed
  736ecc1

• COFF: Add type server pdb files to linkrepro tar file.

  Show description for a29687c
  pcc

  committed
  a29687c

• [Hexagon] Reorganize and update instruction patterns

  Show description for ccf5909
  

  Krzysztof Parzyszek

  committed
  ccf5909

• [X86][SSE] Add missing _mm_extract_ps fast-isel test

  Show description for def1c1f
  RKSimon

  committed
  def1c1f

• [x86] avoid FileCheck assert duplication with retl/retq regex; NFC

  Show description for 8483290
  rotateright

  committed
  8483290

• [X86][SSE] getTargetShuffleMask - check shuffle input value types. NFCI.

  Show description for b29a897
  RKSimon

  committed
  b29a897

• [WebAssembly] MC: Handle (ignore) MCSA_Protected symbol attribute

  Show description for 711a23d
  sbc100

  committed
  711a23d

• Make x86 __ehhandler comdat if parent function is

  Show description for 5854166
  kastiglione

  committed
  5854166

• [Hexagon] Allow redefinition with immediates for hw loop conversion

  Show description for b99a8bc
  

  Krzysztof Parzyszek

  committed
  b99a8bc

• [X86] Check all CPU target names.

  Show description for 268fcdd
  RKSimon

  committed
  268fcdd

• X86 Tests: Add tests for vector permutes with variable indices. NFC.

  Show description for 0c8405a
  

  Zvi Rackover

  committed
  0c8405a

• Revert "[mips] Reordering callseq* nodes to be linear"

  Show description for 88f8f00
  

  Aleksandar Beserminji

  authored and

  Aleksandar Beserminji

  committed
  88f8f00

• [ARM] Use post-RA MI scheduler when +use-misched is set

  Show description for 4eed9af
  eleviant

  committed
  4eed9af

• [X86][AVX512] Regenerate regcall tests.

  Show description for 2d9526e
  RKSimon

  committed
  2d9526e

• [ValueTracking] Enabling ValueTracking patch by default

  Show description for 082e33a
  

  Nikolai Bozhenov

  committed
  082e33a

• Add test case for LoopSink pass

  Show description for 2859100
  

  Max Kazantsev

  committed
  2859100

• [AVR] Fix the select-mbb-placement-bug.ll

  Show description for e536cad
  dylanmckay

  committed
  e536cad

• [ExecutionEngine] Temporarily remove the ExecutionEngine tls tests.

  Show description for dd3a1b1
  lhames

  committed
  dd3a1b1

• [ExecutionEngine] After a heroic dev-meeting hack session, the JIT supports TLS.

  Show description for 801676c
  lhames

  committed
  801676c

• Disabling the transformation introduced in r315888

  Show description for f56176d
  nemanjai

  committed
  f56176d

Commits on Oct 19, 2017

• [XRay] [docs] Document how to generate flamegraphs from xray traces.

  Show description for 4dea1f2
  WiseMaestro

  committed
  4dea1f2

• [Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

  Show description for 5ce470a
  EugeneZelenko

  committed
  5ce470a

• [RISCV] Add missing hunk from r316188

  Show description for 920aa53
  asb

  committed
  920aa53

• [RISCV] Initial codegen support for ALU operations

  Show description for 5a3d179
  asb

  committed
  5a3d179

• [Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

  Show description for ab16d0a
  EugeneZelenko

  committed
  ab16d0a

• [SelectionDAG] Add a check to getVectorShuffle to ensure that the only negative index we allow is -1.

  Show description for fb5a67b
  topperc

  committed
  fb5a67b

• [X86] Remove LowerEXTRACT_SUBVECTOR handler. All EXTRACT_SUBVECTORs are marked as legal.

  Show description for 096ea8c
  topperc

  committed
  096ea8c

• [X86][AES] Test AES intrinsics on 32/64-bit targets with/without VEX encoding

  Show description for d369ce4
  RKSimon

  committed
  d369ce4

• The cost of splitting a large vector instruction is not being taken into account by the getUserCost function. This was leading to some loops being over unrolled. The cost of a vector instruction is…

  Show description for 1f93c85
  

  Graham Yiu

  committed
  1f93c85

• AMDGPU/Docs: Fix unreadable characters

  Show description for cb5868c
  kzhuravl

  committed
  cb5868c

• [Hexagon] Fix store conversion from rr to io in optimize addressing modes

  Show description for 99a0c4c
  

  Krzysztof Parzyszek

  committed
  99a0c4c

• ExecutionEngine: adjust COFF i386 tautological asserts

  Show description for 2ac0f38
  compnerd

  committed
  2ac0f38

• [RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expected

  Show description for 8f5670f
  asb

  committed
  8f5670f

• [RISCV][NFC] Drop unused parameter from createImm helper in RISCVAsmParser

  Show description for 695f682
  asb

  committed
  695f682

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