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vpp: vpp: add g12b support [1/1]
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PD#165090

Problem:
g12b chip bringup

Solution:
add g12b support

Verify:
g12b w400

Change-Id: I9675adcb58737d7b52677fac8d324a100c2c82cd
Signed-off-by: Evoke Zhang <[email protected]>
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Evoke Zhang authored and xiaobo gu committed Jun 25, 2018
1 parent 51a37bc commit 8306932
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Showing 2 changed files with 200 additions and 27 deletions.
59 changes: 32 additions & 27 deletions drivers/vpp/aml_vpp.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -445,7 +445,6 @@ static unsigned int oetf_41_linear_mapping[OSD_OETF_LUT_SIZE] = {
/* 0, 0, 0 mode, right_shift, clip_en */
/*}; */

#ifdef CONFIG_AML_MESON_G12A
static int YUV709l_to_RGB709_coeff12[MATRIX_5x3_COEF_SIZE] = {
-256, -2048, -2048, /* pre offset */
COEFF_NORM12(1.16895), COEFF_NORM12(0.00000), COEFF_NORM12(1.79977),
Expand All @@ -456,7 +455,6 @@ static int YUV709l_to_RGB709_coeff12[MATRIX_5x3_COEF_SIZE] = {
0, 0, 0, /* offset */
0, 0, 0 /* mode, right_shift, clip_en */
};
#endif

#define SIGN(a) ((a < 0) ? "-" : "+")
#define DECI(a) ((a) / 1024)
Expand Down Expand Up @@ -487,10 +485,11 @@ static void vpp_set_matrix_default_init(void)
static void vpp_set_matrix_ycbcr2rgb(int vd1_or_vd2_or_post, int mode)
{
//VPP_PR("%s: %d, %d\n", __func__, vd1_or_vd2_or_post, mode);
#ifdef CONFIG_AML_MESON_G12A

int *m = NULL;

if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) {
if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
(get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B)){
/* POST2 matrix: YUV limit -> RGB default is 12bit*/
m = YUV709l_to_RGB709_coeff12;

Expand All @@ -517,10 +516,9 @@ static void vpp_set_matrix_ycbcr2rgb(int vd1_or_vd2_or_post, int mode)

vpp_reg_setb(VPP_POST2_MATRIX_EN_CTRL, 1, 0, 1);

VPP_PR("g12a post2(bit12) matrix: YUV limit -> RGB ..............\n");
VPP_PR("g12a/b post2(bit12) matrix: YUV limit -> RGB ..............\n");
return;
}
#endif
if (vd1_or_vd2_or_post == 0) { //vd1
vpp_reg_setb(VPP_MATRIX_CTRL, 1, 5, 1);
vpp_reg_setb(VPP_MATRIX_CTRL, 1, 8, 3);
Expand Down Expand Up @@ -962,10 +960,10 @@ for G12A, set osd2 matrix(10bit) RGB2YUV
*/
static void set_osd1_rgb2yuv(bool on)
{
#ifdef CONFIG_AML_MESON_G12A
int *m = NULL;

if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) {
if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
(get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B)){
/* RGB -> 709 limit */
m = RGB709_to_YUV709l_coeff;

Expand All @@ -992,10 +990,8 @@ for G12A, set osd2 matrix(10bit) RGB2YUV

vpp_reg_setb(VPP_WRAP_OSD1_MATRIX_EN_CTRL, on, 0, 1);

VPP_PR("g12a osd1 matrix rgb2yuv ..............\n");
} else
#endif
{
VPP_PR("g12a/b osd1 matrix rgb2yuv ..............\n");
} else {
vpp_reg_setb(VIU_OSD1_BLK0_CFG_W0, 0, 7, 1);
/* eotf lut bypass */
set_vpp_lut(VPP_LUT_OSD_EOTF,
Expand Down Expand Up @@ -1023,12 +1019,12 @@ for G12A, set osd2 matrix(10bit) RGB2YUV
/*
for G12A, set osd2 matrix(10bit) RGB2YUV
*/
static void set_osd2_rgb2yuv(bool on)
{
#ifdef CONFIG_AML_MESON_G12A
static void set_osd2_rgb2yuv(bool on)
{
int *m = NULL;

if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) {
if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
(get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B)){
/* RGB -> 709 limit */
m = RGB709_to_YUV709l_coeff;

Expand All @@ -1055,20 +1051,19 @@ for G12A, set osd2 matrix(10bit) RGB2YUV

vpp_reg_setb(VPP_WRAP_OSD2_MATRIX_EN_CTRL, on, 0, 1);

VPP_PR("g12a osd2 matrix rgb2yuv..............\n");
VPP_PR("g12a/b osd2 matrix rgb2yuv..............\n");
}
#endif
}

/*
for G12A, set osd3 matrix(10bit) RGB2YUV
*/
static void set_osd3_rgb2yuv(bool on)
{
#ifdef CONFIG_AML_MESON_G12A
static void set_osd3_rgb2yuv(bool on)
{
int *m = NULL;

if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) {
if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
(get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B)){
/* RGB -> 709 limit */
m = RGB709_to_YUV709l_coeff;

Expand All @@ -1095,9 +1090,8 @@ for G12A, set osd3 matrix(10bit) RGB2YUV

vpp_reg_setb(VPP_WRAP_OSD3_MATRIX_EN_CTRL, on, 0, 1);

VPP_PR("g12a osd3 matrix rgb2yuv..............\n");
VPP_PR("g12a/b osd3 matrix rgb2yuv..............\n");
}
#endif
}

/*
Expand All @@ -1117,11 +1111,10 @@ static void set_vpp_bitdepth(void)
vpp_reg_setb(VPP_DAT_CONV_PARA1, 0, 0, 14);
#else
#endif
} else if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) {
} else if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
(get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B)){
/*after this step vd1 output data is U12,*/
#ifdef CONFIG_AML_MESON_G12A
vpp_reg_write(DOLBY_PATH_CTRL, 0xf);
#endif
}
}

Expand Down Expand Up @@ -1376,6 +1369,18 @@ void vpp_init(void)
/* 709 limit to RGB */
vpp_set_matrix_ycbcr2rgb(2, 3);
#endif
} else if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) {
/* osd1: rgb->yuv limit,osd2: rgb2yuv limit,osd3: rgb2yuv limit*/
set_osd1_rgb2yuv(1);
set_osd2_rgb2yuv(1);
set_osd3_rgb2yuv(1);

/* set vpp data path to u12 */
set_vpp_bitdepth();
#if (defined CONFIG_AML_LCD)
/* 709 limit to RGB */
vpp_set_matrix_ycbcr2rgb(2, 3);
#endif
} else {
/* set dummy data default YUV black */
vpp_reg_write(VPP_DUMMY_DATA1, 0x108080);
Expand Down
168 changes: 168 additions & 0 deletions drivers/vpp/aml_vpp_reg.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,174 @@
#define VIU_EOTF_LUT_DATA_PORT VPP_EOTF_LUT_DATA_PORT
#endif

/* ********************************
* dummy registers *
* ********************************* */
#ifndef VPP_POST2_MATRIX_PRE_OFFSET0_1
#define VPP_POST2_MATRIX_PRE_OFFSET0_1 0x39ab
#endif

#ifndef VPP_POST2_MATRIX_PRE_OFFSET2
#define VPP_POST2_MATRIX_PRE_OFFSET2 0x39ac
#endif

#ifndef VPP_POST2_MATRIX_COEF00_01
#define VPP_POST2_MATRIX_COEF00_01 0x39a0
#endif

#ifndef VPP_POST2_MATRIX_COEF02_10
#define VPP_POST2_MATRIX_COEF02_10 0x39a1
#endif

#ifndef VPP_POST2_MATRIX_COEF11_12
#define VPP_POST2_MATRIX_COEF11_12 0x39a2
#endif

#ifndef VPP_POST2_MATRIX_COEF20_21
#define VPP_POST2_MATRIX_COEF20_21 0x39a3
#endif

#ifndef VPP_POST2_MATRIX_COEF22
#define VPP_POST2_MATRIX_COEF22 0x39a4
#endif

#ifndef VPP_POST2_MATRIX_OFFSET0_1
#define VPP_POST2_MATRIX_OFFSET0_1 0x39a9
#endif

#ifndef VPP_POST2_MATRIX_OFFSET2
#define VPP_POST2_MATRIX_OFFSET2 0x39aa
#endif

#ifndef VPP_POST2_MATRIX_EN_CTRL
#define VPP_POST2_MATRIX_EN_CTRL 0x39ad
#endif


#ifndef VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1
#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b
#endif

#ifndef VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2
#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c
#endif

#ifndef VPP_WRAP_OSD1_MATRIX_COEF00_01
#define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60
#endif

#ifndef VPP_WRAP_OSD1_MATRIX_COEF02_10
#define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61
#endif

#ifndef VPP_WRAP_OSD1_MATRIX_COEF11_12
#define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62
#endif

#ifndef VPP_WRAP_OSD1_MATRIX_COEF20_21
#define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63
#endif

#ifndef VPP_WRAP_OSD1_MATRIX_COEF22
#define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64
#endif

#ifndef VPP_WRAP_OSD1_MATRIX_OFFSET0_1
#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69
#endif

#ifndef VPP_WRAP_OSD1_MATRIX_OFFSET2
#define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a
#endif

#ifndef VPP_WRAP_OSD1_MATRIX_EN_CTRL
#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1
#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2
#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_COEF00_01
#define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_COEF02_10
#define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_COEF11_12
#define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_COEF20_21
#define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_COEF22
#define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_OFFSET0_1
#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_OFFSET2
#define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a
#endif

#ifndef VPP_WRAP_OSD2_MATRIX_EN_CTRL
#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1
#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2
#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_COEF00_01
#define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_COEF02_10
#define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_COEF11_12
#define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_COEF20_21
#define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_COEF22
#define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_OFFSET0_1
#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_OFFSET2
#define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba
#endif

#ifndef VPP_WRAP_OSD3_MATRIX_EN_CTRL
#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
#endif

#ifndef DOLBY_PATH_CTRL
#define DOLBY_PATH_CTRL 0x1a0c
#endif

/* ********************************
* register access api
* ********************************* */
Expand Down

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