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R600/SI: adjust writemask to only the used components
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Signed-off-by: Christian König <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179165 91177308-0d34-0410-b5e6-96231b3b80d8
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@ChristianKoenigAMD
ChristianKoenigAMD committed Apr 10, 2013
1 parent 9c210da commit 84a775d
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Showing 5 changed files with 156 additions and 33 deletions.
81 changes: 79 additions & 2 deletions lib/Target/R600/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -569,8 +569,9 @@ void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
Operand = SDValue(Node, 0);
}

SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
SelectionDAG &DAG) const {
/// \brief Try to fold the Nodes operands into the Node
SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
SelectionDAG &DAG) const {

// Original encoding (either e32 or e64)
int Opcode = Node->getMachineOpcode();
Expand Down Expand Up @@ -703,3 +704,79 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
return DAG.getMachineNode(Desc->Opcode, Node->getDebugLoc(),
Node->getVTList(), Ops.data(), Ops.size());
}

/// \brief Helper function for adjustWritemask
unsigned SubIdx2Lane(unsigned Idx) {
switch (Idx) {
default: return 0;
case AMDGPU::sub0: return 0;
case AMDGPU::sub1: return 1;
case AMDGPU::sub2: return 2;
case AMDGPU::sub3: return 3;
}
}

/// \brief Adjust the writemask of MIMG instructions
void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
SelectionDAG &DAG) const {
SDNode *Users[4] = { };
unsigned Writemask = 0;

// Try to figure out the used register components
for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
I != E; ++I) {

// Abort if we can't understand the usage
if (!I->isMachineOpcode() ||
I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
return;

unsigned Lane = SubIdx2Lane(I->getConstantOperandVal(1));

// Abort if we have more than one user per component
if (Users[Lane])
return;

Users[Lane] = *I;
Writemask |= 1 << Lane;
}

// Abort if all components are used
if (Writemask == 0xf)
return;

// Adjust the writemask in the node
std::vector<SDValue> Ops;
Ops.push_back(DAG.getTargetConstant(Writemask, MVT::i32));
for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
Ops.push_back(Node->getOperand(i));
Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());

// Update the users of the node with the new indices
for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {

SDNode *User = Users[i];
if (!User)
continue;

SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
DAG.UpdateNodeOperands(User, User->getOperand(0), Op);

switch (Idx) {
default: break;
case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
}
}
}

/// \brief Fold the instructions after slecting them
SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
SelectionDAG &DAG) const {

if (AMDGPU::isMIMG(Node->getMachineOpcode()) != -1)
adjustWritemask(Node, DAG);

return foldOperands(Node, DAG);
}
3 changes: 3 additions & 0 deletions lib/Target/R600/SIISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,9 @@ class SITargetLowering : public AMDGPUTargetLowering {
void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
unsigned RegClass, bool &ScalarSlotUsed) const;

SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;

public:
SITargetLowering(TargetMachine &tm);

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1 change: 1 addition & 0 deletions lib/Target/R600/SIInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,7 @@ namespace AMDGPU {
int getVOPe64(uint16_t Opcode);
int getCommuteRev(uint16_t Opcode);
int getCommuteOrig(uint16_t Opcode);
int isMIMG(uint16_t Opcode);

} // End namespace AMDGPU

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8 changes: 8 additions & 0 deletions lib/Target/R600/SIInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -379,4 +379,12 @@ def getCommuteOrig : InstrMapping {
let ValueCols = [["1"]];
}

def isMIMG : InstrMapping {
let FilterClass = "MIMG_Load_Helper";
let RowFields = ["Inst"];
let ColFields = ["Size"];
let KeyCol = ["8"];
let ValueCols = [["8"]];
}

include "SIInstructions.td"
96 changes: 65 additions & 31 deletions test/CodeGen/R600/llvm.SI.sample.ll
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Original file line number Diff line number Diff line change
@@ -1,21 +1,21 @@
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s

;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE_C
;CHECK: IMAGE_SAMPLE_C
;CHECK: IMAGE_SAMPLE_C
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE_C
;CHECK: IMAGE_SAMPLE_C
;CHECK: IMAGE_SAMPLE_C
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 3
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 2
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 1
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 4
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 8
;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 5
;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 9
;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 6
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 10
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 12
;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 8

define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
Expand Down Expand Up @@ -67,21 +67,55 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
%res16 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v16,
<8 x i32> undef, <4 x i32> undef, i32 16)
%e1 = extractelement <4 x float> %res1, i32 0
%e2 = extractelement <4 x float> %res2, i32 0
%e3 = extractelement <4 x float> %res3, i32 0
%e4 = extractelement <4 x float> %res4, i32 0
%e5 = extractelement <4 x float> %res5, i32 0
%e6 = extractelement <4 x float> %res6, i32 0
%e7 = extractelement <4 x float> %res7, i32 0
%e8 = extractelement <4 x float> %res8, i32 0
%e9 = extractelement <4 x float> %res9, i32 0
%e10 = extractelement <4 x float> %res10, i32 0
%e11 = extractelement <4 x float> %res11, i32 0
%e12 = extractelement <4 x float> %res12, i32 0
%e13 = extractelement <4 x float> %res13, i32 0
%e14 = extractelement <4 x float> %res14, i32 0
%e15 = extractelement <4 x float> %res15, i32 0
%e16 = extractelement <4 x float> %res16, i32 0
%e2 = extractelement <4 x float> %res2, i32 1
%e3 = extractelement <4 x float> %res3, i32 2
%e4 = extractelement <4 x float> %res4, i32 3
%t0 = extractelement <4 x float> %res5, i32 0
%t1 = extractelement <4 x float> %res5, i32 1
%e5 = fadd float %t0, %t1
%t2 = extractelement <4 x float> %res6, i32 0
%t3 = extractelement <4 x float> %res6, i32 2
%e6 = fadd float %t2, %t3
%t4 = extractelement <4 x float> %res7, i32 0
%t5 = extractelement <4 x float> %res7, i32 3
%e7 = fadd float %t4, %t5
%t6 = extractelement <4 x float> %res8, i32 1
%t7 = extractelement <4 x float> %res8, i32 2
%e8 = fadd float %t6, %t7
%t8 = extractelement <4 x float> %res9, i32 1
%t9 = extractelement <4 x float> %res9, i32 3
%e9 = fadd float %t8, %t9
%t10 = extractelement <4 x float> %res10, i32 2
%t11 = extractelement <4 x float> %res10, i32 3
%e10 = fadd float %t10, %t11
%t12 = extractelement <4 x float> %res11, i32 0
%t13 = extractelement <4 x float> %res11, i32 1
%t14 = extractelement <4 x float> %res11, i32 2
%t15 = fadd float %t12, %t13
%e11 = fadd float %t14, %t15
%t16 = extractelement <4 x float> %res12, i32 0
%t17 = extractelement <4 x float> %res12, i32 1
%t18 = extractelement <4 x float> %res12, i32 3
%t19 = fadd float %t16, %t17
%e12 = fadd float %t18, %t19
%t20 = extractelement <4 x float> %res13, i32 0
%t21 = extractelement <4 x float> %res13, i32 2
%t22 = extractelement <4 x float> %res13, i32 3
%t23 = fadd float %t20, %t21
%e13 = fadd float %t22, %t23
%t24 = extractelement <4 x float> %res14, i32 1
%t25 = extractelement <4 x float> %res14, i32 2
%t26 = extractelement <4 x float> %res14, i32 3
%t27 = fadd float %t24, %t25
%e14 = fadd float %t26, %t27
%t28 = extractelement <4 x float> %res15, i32 0
%t29 = extractelement <4 x float> %res15, i32 1
%t30 = extractelement <4 x float> %res15, i32 2
%t31 = extractelement <4 x float> %res15, i32 3
%t32 = fadd float %t28, %t29
%t33 = fadd float %t30, %t31
%e15 = fadd float %t32, %t33
%e16 = extractelement <4 x float> %res16, i32 3
%s1 = fadd float %e1, %e2
%s2 = fadd float %s1, %e3
%s3 = fadd float %s2, %e4
Expand Down

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