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[mips] Add support for -modd-spreg/-mno-odd-spreg
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Summary:
When -mno-odd-spreg is in effect, 32-bit floating point values are not
permitted in odd FPU registers. The option also prohibits 32-bit and 64-bit
floating point comparison results from being written to odd registers.

This option has three purposes:
* It allows support for certain MIPS implementations such as loongson-3a that
  do not allow the use of odd registers for single precision arithmetic.
* When using -mfpxx, -mno-odd-spreg is the default and this allows us to
  statically check that code is compliant with the O32 FPXX ABI since mtc1/mfc1
  instructions to/from odd registers are guaranteed not to appear for any
  reason. Once this has been established, the user can then re-enable
  -modd-spreg to regain the use of all 32 single-precision registers.
* When using -mfp64 and -mno-odd-spreg together, an O32 extension named
  O32 FP64A is used as the ABI. This is intended to provide almost all
  functionality of an FR=1 processor but can also be executed on a FR=0 core
  with the assistance of a hardware compatibility mode which emulates FR=0
  behaviour on an FR=1 processor.

* Added '.module oddspreg' and '.module nooddspreg' each of which update
  the .MIPS.abiflags section appropriately
* Moved setFpABI() call inside emitDirectiveModuleFP() so that the caller
  doesn't have to remember to do it.
* MipsABIFlags now calculates the flags1 and flags2 member on demand rather
  than trying to maintain them in the same format they will be emitted in.

There is one portion of the -mfp64 and -mno-odd-spreg combination that is not
implemented yet. Moves to/from odd-numbered double-precision registers must not
use mtc1. I will fix this in a follow-up.

Differential Revision: http://reviews.llvm.org/D4383


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212717 91177308-0d34-0410-b5e6-96231b3b80d8
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@dsandersllvm
dsandersllvm committed Jul 10, 2014
1 parent a2bc403 commit 24a071b
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Showing 16 changed files with 462 additions and 98 deletions.
108 changes: 77 additions & 31 deletions lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -165,7 +165,8 @@ class MipsAsmParser : public MCTargetAsmParser {
bool parseDirectiveGpDWord();
bool parseDirectiveModule();
bool parseDirectiveModuleFP();
bool parseFpABIValue(Val_GNU_MIPS_ABI &FpABI, StringRef Directive);
bool parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
StringRef Directive);

MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);

Expand Down Expand Up @@ -235,6 +236,9 @@ class MipsAsmParser : public MCTargetAsmParser {
((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);

if (!isABI_O32() && !allowOddSPReg() != 0)
report_fatal_error("-mno-odd-spreg requires the O32 ABI");
}

MCAsmParser &getParser() const { return Parser; }
Expand All @@ -250,6 +254,10 @@ class MipsAsmParser : public MCTargetAsmParser {
bool isABI_O32() const { return STI.getFeatureBits() & Mips::FeatureO32; }
bool isABI_FPXX() const { return false; } // TODO: add check for FeatureXX

bool allowOddSPReg() const {
return !(STI.getFeatureBits() & Mips::FeatureNoOddSPReg);
}

bool inMicroMipsMode() const {
return STI.getFeatureBits() & Mips::FeatureMicroMips;
}
Expand Down Expand Up @@ -563,6 +571,10 @@ class MipsOperand : public MCParsedAsmOperand {
void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
// FIXME: We ought to do this for -integrated-as without -via-file-asm too.
if (!AsmParser.allowOddSPReg() && RegIdx.Index & 1)
AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
"registers");
}

void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
Expand Down Expand Up @@ -2444,7 +2456,7 @@ bool MipsAsmParser::parseSetNoMips16Directive() {
}

bool MipsAsmParser::parseSetFpDirective() {
Val_GNU_MIPS_ABI FpAbiVal;
MipsABIFlagsSection::FpABIKind FpAbiVal;
// Line can be: .set fp=32
// .set fp=xx
// .set fp=64
Expand All @@ -2464,7 +2476,7 @@ bool MipsAsmParser::parseSetFpDirective() {
reportParseError("unexpected token in statement");
return false;
}
getTargetStreamer().emitDirectiveSetFp(FpAbiVal, isABI_O32());
getTargetStreamer().emitDirectiveSetFp(FpAbiVal);
Parser.Lex(); // Consume the EndOfStatement.
return false;
}
Expand Down Expand Up @@ -2784,29 +2796,73 @@ bool MipsAsmParser::parseDirectiveOption() {
return false;
}

/// parseDirectiveModule
/// ::= .module oddspreg
/// ::= .module nooddspreg
/// ::= .module fp=value
bool MipsAsmParser::parseDirectiveModule() {
// Line can be: .module fp=32
// .module fp=xx
// .module fp=64
MCAsmLexer &Lexer = getLexer();
SMLoc L = Lexer.getLoc();

if (!getTargetStreamer().getCanHaveModuleDir()) {
// TODO : get a better message.
reportParseError(".module directive must appear before any code");
return false;
}
AsmToken Tok = Parser.getTok();
if (Tok.isNot(AsmToken::Identifier) && Tok.getString() != "fp") {
reportParseError("unexpected token in .module directive, 'fp' expected");
return false;

if (Lexer.is(AsmToken::Identifier)) {
StringRef Option = Parser.getTok().getString();
Parser.Lex();

if (Option == "oddspreg") {
getTargetStreamer().emitDirectiveModuleOddSPReg(true, isABI_O32());
clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");

if (getLexer().isNot(AsmToken::EndOfStatement)) {
reportParseError("Expected end of statement");
return false;
}

return false;
} else if (Option == "nooddspreg") {
if (!isABI_O32()) {
Error(L, "'.module nooddspreg' requires the O32 ABI");
return false;
}

getTargetStreamer().emitDirectiveModuleOddSPReg(false, isABI_O32());
setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");

if (getLexer().isNot(AsmToken::EndOfStatement)) {
reportParseError("Expected end of statement");
return false;
}

return false;
} else if (Option == "fp") {
return parseDirectiveModuleFP();
}

return Error(L, "'" + Twine(Option) + "' is not a valid .module option.");
}
Parser.Lex(); // Eat fp token
Tok = Parser.getTok();
if (Tok.isNot(AsmToken::Equal)) {

return false;
}

/// parseDirectiveModuleFP
/// ::= =32
/// ::= =xx
/// ::= =64
bool MipsAsmParser::parseDirectiveModuleFP() {
MCAsmLexer &Lexer = getLexer();

if (Lexer.isNot(AsmToken::Equal)) {
reportParseError("unexpected token in statement");
return false;
}
Parser.Lex(); // Eat '=' token.

Val_GNU_MIPS_ABI FpABI;
MipsABIFlagsSection::FpABIKind FpABI;
if (!parseFpABIValue(FpABI, ".module"))
return false;

Expand All @@ -2817,11 +2873,11 @@ bool MipsAsmParser::parseDirectiveModule() {

// Emit appropriate flags.
getTargetStreamer().emitDirectiveModuleFP(FpABI, isABI_O32());

Parser.Lex(); // Consume the EndOfStatement.
return false;
}

bool MipsAsmParser::parseFpABIValue(Val_GNU_MIPS_ABI &FpABI,
bool MipsAsmParser::parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
StringRef Directive) {
MCAsmLexer &Lexer = getLexer();

Expand All @@ -2839,7 +2895,7 @@ bool MipsAsmParser::parseFpABIValue(Val_GNU_MIPS_ABI &FpABI,
return false;
}

FpABI = MipsABIFlagsSection::Val_GNU_MIPS_ABI_FP_XX;
FpABI = MipsABIFlagsSection::FpABIKind::XX;
return true;
}

Expand All @@ -2858,21 +2914,11 @@ bool MipsAsmParser::parseFpABIValue(Val_GNU_MIPS_ABI &FpABI,
return false;
}

FpABI = MipsABIFlagsSection::Val_GNU_MIPS_ABI_FP_DOUBLE;
return true;
} else {
if (isABI_N32() || isABI_N64()) {
FpABI = MipsABIFlagsSection::Val_GNU_MIPS_ABI_FP_DOUBLE;
return true;
}
FpABI = MipsABIFlagsSection::FpABIKind::S32;
} else
FpABI = MipsABIFlagsSection::FpABIKind::S64;

if (isABI_O32()) {
FpABI = MipsABIFlagsSection::Val_GNU_MIPS_ABI_FP_64;
return true;
}

llvm_unreachable("Unknown ABI");
}
return true;
}

return false;
Expand Down
52 changes: 33 additions & 19 deletions lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,16 +11,30 @@

using namespace llvm;

StringRef MipsABIFlagsSection::getFpABIString(Val_GNU_MIPS_ABI Value,
bool Is32BitAbi) {
uint8_t MipsABIFlagsSection::getFpABIValue() {
switch (FpABI) {
case FpABIKind::ANY:
return Val_GNU_MIPS_ABI_FP_ANY;
case FpABIKind::XX:
return Val_GNU_MIPS_ABI_FP_XX;
case FpABIKind::S32:
return Val_GNU_MIPS_ABI_FP_DOUBLE;
case FpABIKind::S64:
if (Is32BitABI)
return OddSPReg ? Val_GNU_MIPS_ABI_FP_64 : Val_GNU_MIPS_ABI_FP_64A;
return Val_GNU_MIPS_ABI_FP_DOUBLE;
default:
return 0;
}
}

StringRef MipsABIFlagsSection::getFpABIString(FpABIKind Value) {
switch (Value) {
case MipsABIFlagsSection::Val_GNU_MIPS_ABI_FP_XX:
case FpABIKind::XX:
return "xx";
case MipsABIFlagsSection::Val_GNU_MIPS_ABI_FP_64:
return "64";
case MipsABIFlagsSection::Val_GNU_MIPS_ABI_FP_DOUBLE:
if (Is32BitAbi)
return "32";
case FpABIKind::S32:
return "32";
case FpABIKind::S64:
return "64";
default:
llvm_unreachable("unsupported fp abi value");
Expand All @@ -30,17 +44,17 @@ StringRef MipsABIFlagsSection::getFpABIString(Val_GNU_MIPS_ABI Value,
namespace llvm {
MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) {
// Write out a Elf_Internal_ABIFlags_v0 struct
OS.EmitIntValue(ABIFlagsSection.getVersion(), 2); // version
OS.EmitIntValue(ABIFlagsSection.getISALevel(), 1); // isa_level
OS.EmitIntValue(ABIFlagsSection.getISARevision(), 1); // isa_rev
OS.EmitIntValue(ABIFlagsSection.getGPRSize(), 1); // gpr_size
OS.EmitIntValue(ABIFlagsSection.getCPR1Size(), 1); // cpr1_size
OS.EmitIntValue(ABIFlagsSection.getCPR2Size(), 1); // cpr2_size
OS.EmitIntValue(ABIFlagsSection.getFpABI(), 1); // fp_abi
OS.EmitIntValue(ABIFlagsSection.getISAExtensionSet(), 4); // isa_ext
OS.EmitIntValue(ABIFlagsSection.getASESet(), 4); // ases
OS.EmitIntValue(ABIFlagsSection.getFlags1(), 4); // flags1
OS.EmitIntValue(ABIFlagsSection.getFlags2(), 4); // flags2
OS.EmitIntValue(ABIFlagsSection.getVersionValue(), 2); // version
OS.EmitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level
OS.EmitIntValue(ABIFlagsSection.getISARevisionValue(), 1); // isa_rev
OS.EmitIntValue(ABIFlagsSection.getGPRSizeValue(), 1); // gpr_size
OS.EmitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1); // cpr1_size
OS.EmitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1); // cpr2_size
OS.EmitIntValue(ABIFlagsSection.getFpABIValue(), 1); // fp_abi
OS.EmitIntValue(ABIFlagsSection.getISAExtensionSetValue(), 4); // isa_ext
OS.EmitIntValue(ABIFlagsSection.getASESetValue(), 4); // ases
OS.EmitIntValue(ABIFlagsSection.getFlags1Value(), 4); // flags1
OS.EmitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2
return OS;
}
}
79 changes: 55 additions & 24 deletions lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,9 +69,17 @@ struct MipsABIFlagsSection {
Val_GNU_MIPS_ABI_FP_ANY = 0,
Val_GNU_MIPS_ABI_FP_DOUBLE = 1,
Val_GNU_MIPS_ABI_FP_XX = 5,
Val_GNU_MIPS_ABI_FP_64 = 6
Val_GNU_MIPS_ABI_FP_64 = 6,
Val_GNU_MIPS_ABI_FP_64A = 7
};

enum AFL_FLAGS1 {
AFL_FLAGS1_ODDSPREG = 1
};

// Internal representation of the values used in .module fp=value
enum class FpABIKind { ANY, XX, S32, S64 };

// Version of flags structure.
uint16_t Version;
// The level of the ISA: 1-5, 32, 64.
Expand All @@ -84,31 +92,52 @@ struct MipsABIFlagsSection {
AFL_REG CPR1Size;
// The size of co-processor 2 registers.
AFL_REG CPR2Size;
// The floating-point ABI.
Val_GNU_MIPS_ABI FpABI;
// Processor-specific extension.
uint32_t ISAExtensionSet;
// Mask of ASEs used.
uint32_t ASESet;

bool OddSPReg;

bool Is32BitABI;

protected:
// The floating-point ABI.
FpABIKind FpABI;

public:
MipsABIFlagsSection()
: Version(0), ISALevel(0), ISARevision(0), GPRSize(AFL_REG_NONE),
CPR1Size(AFL_REG_NONE), CPR2Size(AFL_REG_NONE),
FpABI(Val_GNU_MIPS_ABI_FP_ANY), ISAExtensionSet(0), ASESet(0) {}

uint16_t getVersion() { return (uint16_t)Version; }
uint8_t getISALevel() { return (uint8_t)ISALevel; }
uint8_t getISARevision() { return (uint8_t)ISARevision; }
uint8_t getGPRSize() { return (uint8_t)GPRSize; }
uint8_t getCPR1Size() { return (uint8_t)CPR1Size; }
uint8_t getCPR2Size() { return (uint8_t)CPR2Size; }
uint8_t getFpABI() { return (uint8_t)FpABI; }
uint32_t getISAExtensionSet() { return (uint32_t)ISAExtensionSet; }
uint32_t getASESet() { return (uint32_t)ASESet; }
uint32_t getFlags1() { return 0; }
uint32_t getFlags2() { return 0; }

StringRef getFpABIString(Val_GNU_MIPS_ABI Value, bool Is32BitAbi);
CPR1Size(AFL_REG_NONE), CPR2Size(AFL_REG_NONE), ISAExtensionSet(0),
ASESet(0), OddSPReg(false), Is32BitABI(false), FpABI(FpABIKind::ANY) {}

uint16_t getVersionValue() { return (uint16_t)Version; }
uint8_t getISALevelValue() { return (uint8_t)ISALevel; }
uint8_t getISARevisionValue() { return (uint8_t)ISARevision; }
uint8_t getGPRSizeValue() { return (uint8_t)GPRSize; }
uint8_t getCPR1SizeValue() { return (uint8_t)CPR1Size; }
uint8_t getCPR2SizeValue() { return (uint8_t)CPR2Size; }
uint8_t getFpABIValue();
uint32_t getISAExtensionSetValue() { return (uint32_t)ISAExtensionSet; }
uint32_t getASESetValue() { return (uint32_t)ASESet; }

uint32_t getFlags1Value() {
uint32_t Value = 0;

if (OddSPReg)
Value |= (uint32_t)AFL_FLAGS1_ODDSPREG;

return Value;
}

uint32_t getFlags2Value() { return 0; }

FpABIKind getFpABI() { return FpABI; }
void setFpABI(FpABIKind Value, bool IsABI32Bit) {
FpABI = Value;
Is32BitABI = IsABI32Bit;
}
StringRef getFpABIString(FpABIKind Value);

template <class PredicateLibrary>
void setISALevelAndRevisionFromPredicates(const PredicateLibrary &P) {
Expand Down Expand Up @@ -177,16 +206,18 @@ struct MipsABIFlagsSection {

template <class PredicateLibrary>
void setFpAbiFromPredicates(const PredicateLibrary &P) {
FpABI = Val_GNU_MIPS_ABI_FP_ANY;
Is32BitABI = P.isABI_O32();

FpABI = FpABIKind::ANY;
if (P.isABI_N32() || P.isABI_N64())
FpABI = Val_GNU_MIPS_ABI_FP_DOUBLE;
FpABI = FpABIKind::S64;
else if (P.isABI_O32()) {
if (P.isFP64bit())
FpABI = Val_GNU_MIPS_ABI_FP_64;
FpABI = FpABIKind::S64;
else if (P.isABI_FPXX())
FpABI = Val_GNU_MIPS_ABI_FP_XX;
FpABI = FpABIKind::XX;
else
FpABI = Val_GNU_MIPS_ABI_FP_DOUBLE;
FpABI = FpABIKind::S32;
}
}

Expand Down
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