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drm/amd/display: Investigate tool reported FCLK P-state deviations
[Why] Fix for some of the tool reported modes for FCLK P-state deviations and UCLK P-state deviations that are coming from DSC terms and/or Scaling terms causing MinActiveFCLKChangeLatencySupported and MaxActiveDRAMClockChangeLatencySupported incorrectly calculated in DML for these configurations. Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Nevenko Stupar <[email protected]> Tested-by: Mark Broadworth <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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