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Commits on Mar 19, 2016

• Copyright fix

  kraigher

  committed
  58612be

• Increased length of runner_cfg_default to the maximum for runner_cfg to work with Incisive. Generally removed the default value from testbenches but kept it in examples where it's explicitly discus…

  Show description for a48d663
  

  LarsAsplund

  authored and

  kraigher

  committed
  a48d663

• Deprecated runner_cfg_t.

  

  LarsAsplund

  authored and

  kraigher

  committed
  6916ee5

• Removed some VHDL 2008 constructs unknown to Incisive.

  

  LarsAsplund

  authored and

  kraigher

  committed
  5054857

Commits on Feb 13, 2016

• Copyright

  kraigher

  committed
  c64bc88

Commits on Feb 12, 2016

• Merge pull request VUnit#124 from cmarqu/patch-3

  Show description for 5330f6a
  LarsAsplund

  committed
  5330f6a

• Merge pull request VUnit#123 from cmarqu/patch-2

  Show description for 3ea5a2f
  LarsAsplund

  committed
  3ea5a2f

• Typofix.

  

  Colin Marquardt

  committed
  2a110eb

• Comment improvements.

  

  Colin Marquardt

  committed
  6632471

• Comment improvements.

  

  Colin Marquardt

  committed
  68d6b42

Commits on Feb 6, 2016

• Made get_compile_order public

  kraigher

  committed
  c94e2a9

Commits on Jan 28, 2016

• Copyright

  kraigher

  committed
  0add5bd

Commits on Jan 26, 2016

• Updated links to old repository.

  LarsAsplund

  committed
  81deba3

Commits on Dec 12, 2015

• Fixed broken OSVVM integration test cases

  LarsAsplund

  committed
  3f5f023

Commits on Oct 25, 2015

• Moved vhdl/verilog into vunit package folder

  kraigher

  committed
  c55b8ce

Commits on Oct 24, 2015

• Added example of UVVM integration.

  LarsAsplund

  committed
  eeb6e09

Commits on Sep 22, 2015

• Made OSVVM integration tests run with Active-HDL

  

  LarsAsplund

  authored and

  kraigher

  committed
  2bb8b99

Commits on Sep 20, 2015

• Added workaround to make tb_card_shuffler.vhd example work with Aldec.

  

  LarsAsplund

  authored and

  kraigher

  committed
  8a769af

• Fix set call that Aldec simulator considers ambiguous

  kraigher

  committed
  7f6e46d

Commits on Sep 5, 2015

• Mixed BVUL and VUnit check and log functionality.

  LarsAsplund

  committed
  da941c7

• Simplified BVUL integration and added first example.

  LarsAsplund

  committed
  3bbde36

Commits on Sep 1, 2015

• Fixed license header

  kraigher

  committed
  e3eae14

Commits on Aug 28, 2015

• Added hooks to extract compile order correct dependencies for a specified target within a VUnit project. Includes example of doing this.

  

  joshrsmith

  authored and

  kraigher

  committed
  f76b4a2

Commits on Jun 30, 2015

• Moving vhdl examples into examples/vhdl/

  Show description for d714fcc
  kraigher

  committed
  d714fcc

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