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Commits on Jul 24, 2022

• merge master

  jjts

  committed
  668842a

Commits on Jul 11, 2022

• Update Verrilator cpp testbench;

  PedroAntunes178

  committed
  0cd628e

Commits on Jul 5, 2022

• add qsys memory controller subsystem

  jjts

  committed
  f42f237

Commits on Jun 17, 2022

• Update git ignore console files;

  PedroAntunes178

  committed
  528bb87

Commits on May 31, 2022

• remove ASIC folders and references

  JDLopes

  committed
  0c8e9ab

Commits on Mar 10, 2022

• fix .gitignore file; add verilator to simulation tests; cleanup simulation.mk file; remove debug code lines from testbenches; fix console; add test.expected file for verilator

  JDLopes

  committed
  234bc6b

Commits on Mar 9, 2022

• update .gitignore file; add sw-clean to hw-clean target; fix software clean targets

  JDLopes

  committed
  6b19732

Commits on Mar 8, 2022

• feat(Modelsim): Add modelsim makefile and script

  Show description for 6c76035
  P-Miranda

  committed
  6c76035

Commits on Feb 16, 2022

• switched to devel for future work from now on

  microSharjeel

  committed
  cabcca5

Commits on Jan 26, 2022

• unignore verilog_tb

  jjts

  committed
  79bdb41

Commits on Nov 28, 2021

• Merge branch 'corename' of github.com:JDLopes/iob-soc

  JDLopes

  committed
  befb4a1

Commits on Nov 22, 2021

• remove fpga los from gitignore

  jjts

  committed
  a87fb77

Commits on Nov 19, 2021

• readme comments marked with // and small makefile changes

  jjts

  committed
  d59fe6e

Commits on Nov 18, 2021

• fix ignore

  jjts

  committed
  26faa5e

Commits on Oct 19, 2021

• improve Makefiles for ASIC; change initial.v file name to initial_sram.v; update .gitignore file

  JDLopes

  committed
  a7285e3

Commits on Oct 11, 2021

• use --delete flag on clean-remote targets only; fix .gitignore file; minor improvements in FPGAs' Makefiles

  JDLopes

  committed
  f397a29

Commits on Oct 6, 2021

• add clean targets for cleanning remote and testlog; move initial.v file for verilog directory in hardware/asic/umc130; update .gitignore file; add targets for ASIC recursive testing in root Makefil…

  Show description for 6858ad7
  JDLopes

  committed
  6858ad7

Commits on Oct 5, 2021

• move general targets from umc130 Makefile to asic.mk; add first files for umc130 synthesis; update .gitignore file

  JDLopes

  committed
  f1776d8

• update .gitignore file

  JDLopes

  committed
  30e4648

Commits on Oct 4, 2021

• add framework to generate ASIC memories; update .gitignore file

  JDLopes

  committed
  8070d2e

Commits on Oct 3, 2021

• remove test report to facilitate ci/cd

  jjts

  committed
  738e71f

Commits on Aug 26, 2021

• a few more refactorisations

  jjts

  committed
  b1b8ad5

Commits on Aug 25, 2021

• all tests passing

  jjts

  committed
  8c9fe9e

• fix tests and document gen

  jjts

  committed
  684d073

Commits on Aug 22, 2021

• progress commit

  jjts

  committed
  367a051

Commits on Aug 18, 2021

• fixing board access queue: not working yet

  jjts

  committed
  3b42948

Commits on Jun 30, 2021

• updating readme and presentation (wip)

  jjts

  committed
  627f554

Commits on May 29, 2021

• fix pc-emul

  jjts

  committed
  badd559

• fixes for remote fpga compile

  jjts

  committed
  49cb405

Commits on May 28, 2021

• makefile revamp

  jjts

  committed
  fb10c1b

Commits on Apr 1, 2021

• fixed wrong path to ku040 board directory

  AndreMerendeira

  committed
  903d17e

• updated gitignore to ignore synthesis files in DE10 and ku040 boards

  AndreMerendeira

  committed
  5741398

Commits on Feb 18, 2021

• merge verilator branch

  jjts

  committed
  1421763

• merge devel cache, delete system_config.mk

  jjts

  committed
  fe2fd85

Commits on Feb 11, 2021

• console and boot exchanging files

  jjts

  committed
  84db182

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