64-bit RISC-V processor
The project is implemented for the TEKNOFEST Chip Design Contest held every year in Turkey. RISC-V
processor core and UART, SPI peripherals are all designed from the ground up. The core supports
I(Integer), M(Multiply-divide), C(Compressed), and 6 other special instructions. The complete SoC can run at
100 MHz in Artix-7 FPGA and is tested on the Arty A7 35T FPGA board.
What you see in the photo below is printed by the processor I designed. 