- 💬 Ask me about VHDL, Verilog, SystemVerilog, UVM, FPGA, RISC-V, C++
- 📫 How to reach me: LinkedIn https://www.linkedin.com/in/muhammedkocaoglu/
🎯
Focusing
Digital Design Engineer
Popular repositories Loading
-
-
SystemVerilog-Tutorials
SystemVerilog-Tutorials PublicSystemVerilog derslerinde yazdığım kodları içermektedir.
-
-
Digital-Clock-on-VGA-800x600-using-VHDL-and-FPGA
Digital-Clock-on-VGA-800x600-using-VHDL-and-FPGA PublicVHDL 4
-
A-GUI-to-Perform-IEEE-754-Single-and-Double-Precision-Arithmetics
A-GUI-to-Perform-IEEE-754-Single-and-Double-Precision-Arithmetics Public -
Fully-Pipelined-Edge-Detector-Algorithms-Using-VHDL
Fully-Pipelined-Edge-Detector-Algorithms-Using-VHDL PublicRoberts, Prewitt, Scharr, and Sobel edge detector algorithms
VHDL 4
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.