History for lib - tzlaine/llvm

[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.

brads55

committed

[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.

brads55

committed

[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.

brads55

committed

[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.

brads55

committed

[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.

brads55

committed

[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.

brads55

committed

[ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly.

brads55

committed

[ARM64] Remove PrefetchOp and use ARM64PRFM instead.

brads55

committed

[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.

brads55

committed

[ARM64] Remove ARM64SYS.

brads55

committed

[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.

brads55

committed

[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.

brads55

committed

[ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.

brads55

committed

[ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're cu…

brads55

committed

[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.

brads55

committed

[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)

brads55

committed

[ARM64] Add missing 1Q -> 1q vector kind alias

brads55

committed

[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}

brads55

committed

[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX

brads55

committed

[ARM64] STRHro and STRBro were not being decoded at all.

brads55

committed

[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.

brads55

committed

[ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.

brads55

committed

Revert "YAMLIO: Encode ambiguous hex strings explicitly"

filcab

committed

SLPVectorizer: Only vectorize intrinsics whose operands are widened equally

aschwaighofer

committed

AVX-512: insert element to mask vector; store i1 data

Elena Demikhovsky

committed

Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math

dsandersllvm

committed

YAMLIO: Encode ambiguous hex strings explicitly

majnemer

committed

Delinearize: Extend informationin -analyze output

tobiasgrosser

committed

R600/SI: Match not instruction.

arsenm

committed

ARM64: scalarize v1i64 mul operation

TNorthover

committed

ARM64: add pattern for <1 x i64> custom not node.

TNorthover

committed

Object: add type names for ARM/COFF relocations

compnerd

committed

ARM MC: 80 column

compnerd

committed

ARM MC: sort source files in CMakeLists

compnerd

committed

[C++11] More 'nullptr' conversion or in some cases just using a boolean check instead of comparing to nullptr.

topperc

committed

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Commits on Apr 9, 2014

[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.

[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.

[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.

[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.

[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.

[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value.

[ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly.

[ARM64] Remove PrefetchOp and use ARM64PRFM instead.

[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.

[ARM64] Remove ARM64SYS.

[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.

[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.

[ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.

[ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're cu…

[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.

[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)

[ARM64] Add missing 1Q -> 1q vector kind alias

[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}

[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX

[ARM64] STRHro and STRBro were not being decoded at all.

[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.

[ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined.

Revert "YAMLIO: Encode ambiguous hex strings explicitly"

SLPVectorizer: Only vectorize intrinsics whose operands are widened equally

AVX-512: insert element to mask vector; store i1 data

Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of -enable-no-nans-fp-math

YAMLIO: Encode ambiguous hex strings explicitly

Delinearize: Extend informationin -analyze output

R600/SI: Match not instruction.

ARM64: scalarize v1i64 mul operation

ARM64: add pattern for <1 x i64> custom not node.

Object: add type names for ARM/COFF relocations

ARM MC: 80 column

ARM MC: sort source files in CMakeLists

[C++11] More 'nullptr' conversion or in some cases just using a boolean check instead of comparing to nullptr.

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Commits on Apr 9, 2014

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