Skip to content

Commit

Permalink
[Arm64] ASIMD Miscellaneous (dotnet#38110)
Browse files Browse the repository at this point in the history 
* AbsSaturate and AbsSaturateScalar

* AddAcrossWidening

* AddSaturate and AddSaturateScalar (suqadd and usqadd)

* Ceiling and CeilingScalar

* ConvertToDoubleScalar

* ConvertToDoubleUpper

* ConvertToInt32RoundAwayFromZero and ConvertToInt32RoundAwayFromZeroScalar

* ConvertToInt32RoundToEven and ConvertToInt32RoundToEvenScalar

* ConvertToInt32RoundToNegativeInfinity and ConvertToInt32RoundToNegativeInfinityScalar

* ConvertToInt32RoundToPositiveInfinity and ConvertToInt32RoundToPositiveInfinityScalar

* ConvertToInt32RoundToZero and ConvertToInt32RoundToZeroScalar

* ConvertToInt64RoundAwayFromZero and ConvertToInt64RoundAwayFromZeroScalar

* ConvertToInt64RoundToEven and ConvertToInt64RoundToEvenScalar

* ConvertToInt64RoundToNegativeInfinity and ConvertToInt64RoundToNegativeInfinityScalar

* ConvertToInt64RoundToPositiveInfinity and ConvertToInt64RoundToPositiveInfinityScalar

* ConvertToInt64RoundToZero and ConvertToInt64RoundToZeroScalar

* ConvertToSingle and ConvertToSingleScalar

* ConvertToUInt32RoundAwayFromZero and ConvertToUInt32RoundAwayFromZeroScalar

* ConvertToUInt32RoundToEven and ConvertToUInt32RoundToEvenScalar

* ConvertToUInt32RoundToNegativeInfinity and ConvertToUInt32RoundToNegativeInfinityScalar

* ConvertToUInt32RoundToPositiveInfinity and ConvertToUInt32RoundToPositiveInfinityScalar

* ConvertToUInt32RoundToZero and ConvertToUInt32RoundToZeroScalar

* ConvertToUInt64RoundAwayFromZero and ConvertToUInt64RoundAwayFromZeroScalar

* ConvertToUInt64RoundToEven and ConvertToUInt64RoundToEvenScalar

* ConvertToUInt64RoundToNegativeInfinity and ConvertToUInt64RoundToNegativeInfinityScalar

* ConvertToUInt64RoundToPositiveInfinity and ConvertToUInt64RoundToPositiveInfinityScalar

* ConvertToUInt64RoundToZero and ConvertToUInt64RoundToZeroScalar

* Floor and FloorScalar

* NegateSaturate and NegateSaturateScalar

* RoundAwayFromZero and RoundAwayFromZeroScalar

* RoundToNearest and RoundToNearestScalar

* RoundToNegativeInfinity and RoundToNegativeInfinityScalar

* RoundToPositiveInfinity and RoundToPositiveInfinityScalar

* RoundToZero and RoundToZeroScalar
  • Loading branch information
@echesakov
echesakov authored Jun 19, 2020
1 parent 7d5dd34 commit 63c60f1
Show file tree
Hide file tree
Showing 212 changed files with 81,893 additions and 1,340 deletions.
6 changes: 5 additions & 1 deletion src/coreclr/src/jit/emitarm64.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12549,7 +12549,7 @@ void emitter::emitDispIns(
emitDispVectorReg(id->idReg1(), optWidenElemsize(id->idInsOpt()), true);
emitDispVectorReg(id->idReg2(), id->idInsOpt(), false);
}
else if ((ins == INS_fcvtn) || (ins == INS_fcvtn2))
else if ((ins == INS_fcvtn) || (ins == INS_fcvtn2) || (ins == INS_fcvtxn) || (ins == INS_fcvtxn2))
{
emitDispVectorReg(id->idReg1(), id->idInsOpt(), true);
emitDispVectorReg(id->idReg2(), optWidenElemsize(id->idInsOpt()), false);
Expand Down Expand Up @@ -12679,6 +12679,10 @@ void emitter::emitDispIns(
emitDispReg(id->idReg2(), elemsize, true);
emitDispImm(0, false);
}
else if (ins == INS_fcvtxn)
{
emitDispReg(id->idReg2(), EA_8BYTE, false);
}
else
{
emitDispReg(id->idReg2(), elemsize, false);
Expand Down
5 changes: 5 additions & 0 deletions src/coreclr/src/jit/hwintrinsic.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1023,6 +1023,11 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op1ClsHnd));
break;

case NI_AdvSimd_Arm64_AddSaturateScalar:
assert(varTypeIsSIMD(op2->TypeGet()));
retNode->AsHWIntrinsic()->SetAuxiliaryType(getBaseTypeOfSIMDType(sigReader.op2ClsHnd));
break;

default:
break;
}
Expand Down
18 changes: 18 additions & 0 deletions src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -735,6 +735,24 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
break;

case NI_AdvSimd_Arm64_AddSaturateScalar:
if (varTypeIsUnsigned(node->GetAuxiliaryType()) != varTypeIsUnsigned(intrin.baseType))
{
ins = varTypeIsUnsigned(intrin.baseType) ? INS_usqadd : INS_suqadd;

if (targetReg != op1Reg)
{
GetEmitter()->emitIns_R_R(INS_mov, emitTypeSize(node), targetReg, op1Reg);
}

GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op2Reg, opt);
}
else
{
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
}
break;

// mvni doesn't support the range of element types, so hard code the 'opts' value.
case NI_Vector64_get_Zero:
case NI_Vector64_get_AllBitsSet:
Expand Down
82 changes: 79 additions & 3 deletions src/coreclr/src/jit/hwintrinsiclistarm64.h
View file

Large diffs are not rendered by default.

6 changes: 3 additions & 3 deletions src/coreclr/src/jit/simdashwintrinsiclistarm64.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -94,13 +94,13 @@ SIMD_AS_HWINTRINSIC_ID(Vector4, SquareRoot,
// Vector<T> Intrinsics
SIMD_AS_HWINTRINSIC_ID(VectorT128, Abs, 1, {NI_AdvSimd_Abs, NI_VectorT128_Abs, NI_AdvSimd_Abs, NI_VectorT128_Abs, NI_AdvSimd_Abs, NI_VectorT128_Abs, NI_AdvSimd_Arm64_Abs, NI_VectorT128_Abs, NI_AdvSimd_Abs, NI_AdvSimd_Arm64_Abs}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, AndNot, 2, {NI_AdvSimd_BitwiseClear, NI_AdvSimd_BitwiseClear, NI_AdvSimd_BitwiseClear, NI_AdvSimd_BitwiseClear, NI_AdvSimd_BitwiseClear, NI_AdvSimd_BitwiseClear, NI_AdvSimd_BitwiseClear, NI_AdvSimd_BitwiseClear, NI_AdvSimd_BitwiseClear, NI_AdvSimd_BitwiseClear}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, Ceiling, 1, {NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_AdvSimd_Ceiling, NI_AdvSimd_Ceiling}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, Ceiling, 1, {NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_AdvSimd_Ceiling, NI_AdvSimd_Arm64_Ceiling}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, ConditionalSelect, 3, {NI_VectorT128_ConditionalSelect, NI_VectorT128_ConditionalSelect, NI_VectorT128_ConditionalSelect, NI_VectorT128_ConditionalSelect, NI_VectorT128_ConditionalSelect, NI_VectorT128_ConditionalSelect, NI_VectorT128_ConditionalSelect, NI_VectorT128_ConditionalSelect, NI_VectorT128_ConditionalSelect, NI_VectorT128_ConditionalSelect}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, Equals, 2, {NI_AdvSimd_CompareEqual, NI_AdvSimd_CompareEqual, NI_AdvSimd_CompareEqual, NI_AdvSimd_CompareEqual, NI_AdvSimd_CompareEqual, NI_AdvSimd_CompareEqual, NI_AdvSimd_Arm64_CompareEqual, NI_AdvSimd_Arm64_CompareEqual, NI_AdvSimd_CompareEqual, NI_AdvSimd_Arm64_CompareEqual}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_NM(VectorT128, EqualsInstance, "Equals", 2, {NI_Vector128_op_Equality, NI_Vector128_op_Equality, NI_Vector128_op_Equality, NI_Vector128_op_Equality, NI_Vector128_op_Equality, NI_Vector128_op_Equality, NI_Vector128_op_Equality, NI_Vector128_op_Equality, NI_Vector128_op_Equality, NI_Vector128_op_Equality}, SimdAsHWIntrinsicFlag::InstanceMethod)
SIMD_AS_HWINTRINSIC_ID(VectorT128, Floor, 1, {NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_AdvSimd_Floor, NI_AdvSimd_Floor}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, Floor, 1, {NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_Illegal, NI_AdvSimd_Floor, NI_AdvSimd_Arm64_Floor}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, get_AllBitsSet, 0, {NI_Vector128_get_AllBitsSet, NI_Vector128_get_AllBitsSet, NI_Vector128_get_AllBitsSet, NI_Vector128_get_AllBitsSet, NI_Vector128_get_AllBitsSet, NI_Vector128_get_AllBitsSet, NI_Vector128_get_AllBitsSet, NI_Vector128_get_AllBitsSet, NI_Vector128_get_AllBitsSet, NI_Vector128_get_AllBitsSet}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, get_Count, 0, {NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, get_Count, 0, {NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count, NI_VectorT128_get_Count}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, get_Zero, 0, {NI_Vector128_get_Zero, NI_Vector128_get_Zero, NI_Vector128_get_Zero, NI_Vector128_get_Zero, NI_Vector128_get_Zero, NI_Vector128_get_Zero, NI_Vector128_get_Zero, NI_Vector128_get_Zero, NI_Vector128_get_Zero, NI_Vector128_get_Zero}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, GreaterThan, 2, {NI_AdvSimd_CompareGreaterThan, NI_AdvSimd_CompareGreaterThan, NI_AdvSimd_CompareGreaterThan, NI_AdvSimd_CompareGreaterThan, NI_AdvSimd_CompareGreaterThan, NI_AdvSimd_CompareGreaterThan, NI_AdvSimd_Arm64_CompareGreaterThan, NI_AdvSimd_Arm64_CompareGreaterThan, NI_AdvSimd_CompareGreaterThan, NI_AdvSimd_Arm64_CompareGreaterThan}, SimdAsHWIntrinsicFlag::None)
SIMD_AS_HWINTRINSIC_ID(VectorT128, GreaterThanOrEqual, 2, {NI_AdvSimd_CompareGreaterThanOrEqual, NI_AdvSimd_CompareGreaterThanOrEqual, NI_AdvSimd_CompareGreaterThanOrEqual, NI_AdvSimd_CompareGreaterThanOrEqual, NI_AdvSimd_CompareGreaterThanOrEqual, NI_AdvSimd_CompareGreaterThanOrEqual, NI_AdvSimd_Arm64_CompareGreaterThanOrEqual, NI_AdvSimd_Arm64_CompareGreaterThanOrEqual, NI_AdvSimd_CompareGreaterThanOrEqual, NI_AdvSimd_Arm64_CompareGreaterThanOrEqual}, SimdAsHWIntrinsicFlag::None)
Expand Down
Loading

0 comments on commit 63c60f1

Please sign in to comment.