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echesakov

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Commits on Jul 30, 2020

• Consider that retbuf arg can point to GC heap in fgCreateCallDispatcherAndGetResult() (dotnet#39815)

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  echesakov

  authored
  1e23a06

Commits on Jul 25, 2020

• [Arm64] Don't generate hardware intrinsic method bodies (dotnet#39753)

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  echesakov

  authored
  84eeebb

Commits on Jul 24, 2020

• Fix issues with JitStressRange (dotnet#39754)

  Show description for 8782d4b
  echesakov

  authored
  8782d4b

Commits on Jul 14, 2020

• [Arm64] ASIMD StorePair StorePairNonTemporal (dotnet#39240)

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  echesakov

  authored
  43b2578

Commits on Jul 13, 2020

• [Arm64] ASIMD DotProduct and Rounding Double Multiply Add/Subtract (dotnet#38957)

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  echesakov

  authored
  d9a7d8f

Commits on Jul 7, 2020

• [Arm64] ASIMD ReverseElement8 ReverseElement16 ReverseElement32 (dotnet#38850)

  echesakov

  authored
  a014fbd

• [Arm64] ASIMD MultiplyDoubling* and MultiplyRoundedDoubling* intrinsics (dotnet#38725)

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  echesakov

  authored
  ccc34b3

Commits on Jul 2, 2020

• [Arm64] ASIMD InsertScalar and rename to ShiftLeftAndInsert ShiftRightAndInsert (dotnet#38680)

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  echesakov

  authored
  eaf3c78

Commits on Jun 30, 2020

• [Arm64] ASIMD ExtractNarrowingSaturate and ExtractNarrowingSaturateUnsigned (dotnet#38371)

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  echesakov

  authored
  d42d28b

Commits on Jun 25, 2020

• [Arm64] Implement remaining SIMD instructions (dotnet#38361)

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  echesakov

  authored
  eb30d2a

Commits on Jun 22, 2020

• [Arm64] Vector64<double>.CreateScalar, Vector64<ulong>CreateScalar and Vector64<long>.CreateScalar (dotnet#38139)

  echesakov

  authored
  ab119ad

Commits on Jun 19, 2020

• [Arm64] ASIMD Miscellaneous (dotnet#38110)

  Show description for 63c60f1
  echesakov

  authored
  63c60f1

Commits on Jun 18, 2020

• [Arm64] Implement fcvtxn, fcvtxn2, sqabs, sqneg, suqadd, usqadd (dotnet#38010)

  echesakov

  authored
  cf7ce3b

Commits on Jun 17, 2020

• [Arm64] ASIMD By Element Intrinsics (dotnet#36916)

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  echesakov

  authored
  a23d3b2

Commits on May 23, 2020

• [Arm64] ASIMD Shift Intrinsics (dotnet#36830)

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  echesakov

  authored
  a26363e

Commits on May 22, 2020

• [Arm64] Follow-up on renaming intrinsics to Narrowing for consistency with Widening (dotnet#36857)

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  echesakov

  authored
  d81a276

• [Arm64] Polynomial Multiply Long Intrinsics (dotnet#36853)

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  echesakov

  authored
  1c18e8c

Commits on May 21, 2020

• [Arm64] ASIMD Shift instructions (dotnet#36552)

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  echesakov

  authored
  bdc0943

Commits on May 7, 2020

• [Arm64] ASIMD Rename AddReturningHighNarrow to AddHighNarrow (dotnet#35919)

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  echesakov

  authored
  08b244e

Commits on May 1, 2020

• [Arm64] Fix JIT/HardwareIntrinsics/Arm/AdvSimd tests (dotnet#35726)

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  echesakov

  authored
  44a3313

• [Arm64] Implement ASIMD widening, narrowing, saturating intrinsics (dotnet#35612)

  Show description for a156293
  echesakov

  authored
  a156293

Commits on Apr 30, 2020

• [Arm64] Implement Vector64/128.CreateScalar() using AdvSimd.Insert (dotnet#35300)

  echesakov

  authored
  670bf21

• Remove HW_Flag_UnfixedSIMDSize (dotnet#35594)

  Show description for 1f436e0
  echesakov

  authored
  1f436e0

Commits on Apr 29, 2020

• [Arm64] Implement ASIMD widening, narrowing, saturating instructions (dotnet#35379)

  echesakov

  authored
  f03d585

Commits on Apr 22, 2020

• [Arm64] Implement ASIMD Extract Insert ExtractVector64 ExtractVector128 (dotnet#35030)

  Show description for 32dd7d4
  echesakov

  authored
  32dd7d4

Commits on Apr 9, 2020

• [Arm64] Change uint to Vector64<uint> in Sha1 intrinsics (dotnet#34730)

  Show description for 3838fb7
  echesakov

  authored
  3838fb7

• [Arm64] Simplify logic for RMW hardware intrinsics (dotnet#34668)

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  echesakov

  authored
  eac13ca

Commits on Mar 26, 2020

• Unconditionally enable InstructionSet_ArmBase in PAL_GetJitCpuCapabilityFlags in src/coreclr/src/pal/src/misc/jitsupport.cpp (dotnet#34107)

  echesakov

  authored
  24e10f6

Commits on Mar 24, 2020

• [Arm64] Implement more hardware intrinsics as proposed in dotnet#24794 (dotnet#33889)

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  echesakov

  authored
  eff3797

Commits on Mar 19, 2020

• [Arm64] Implement Store Hardware Intrinsic (dotnet#33535)

  echesakov

  authored
  beb6a26

Commits on Mar 14, 2020

• [Arm64] Vector Load/Store structure instructions (dotnet#33461)

  Show description for 6b8cda0
  echesakov

  authored
  6b8cda0

Commits on Feb 21, 2020

• [Arm64] AddAcross MaxAcross MinAcross MaxNumber MaxNumberPairwise MaxPairwise (dotnet#32620)

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  echesakov

  authored
  9981b1f

Commits on Feb 14, 2020

• [Arm64] Add ASIMD pairwise reduce instructions (dotnet#32277)

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  echesakov

  authored
  28054c6

Commits on Feb 11, 2020

• [Arm64] Implement FMA, FMS, MLA, MLS (dotnet#31899)

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  echesakov

  authored
  7b58790

Commits on Feb 5, 2020

• [Arm64] Implement simple SIMD operations (dotnet#1601)

  Show description for c44edc1
  echesakov

  authored
  c44edc1

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