Must-have verilog systemverilog modules

BaseJump STL: A Standard Template Library for SystemVerilog

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Technically-oriented PDF Collection (Papers, Specs, Decks, Manuals, etc)

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

Advanced Architecture Labs with CVA6

Lean but mean RISC-V system!

Let's write an OS which can run on RISC-V in Rust from scratch!

RISC-V CPU Core

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

Repository to host and maintain scale-sim-v2 code

A List of Free and Open Source Hardware Verification Tools and Frameworks

Berkeley's Spatial Array Generator

Spike, a RISC-V ISA Simulator

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at…

Verilog parser, preprocessor, and related tools for the Verilog-Perl package

GPGPU microprocessor architecture

lowRISC Style Guides

Google AI 2018 BERT pytorch implementation