Stars
xk265:HEVC/H.265 Video Encoder IP Core (RTL)
Reference implementation of Megalodon 7B model
Fast and memory-efficient exact attention
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
🚧 (Alpha stage software) Edit files, run programs, and work with LSP on a remote machine from the comfort of your local environment 🚧
Modular visual interface for GDB in Python
Verilog parser, preprocessor, and related tools for the Verilog-Perl package
A machine learning compiler for GPUs, CPUs, and ML accelerators
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
mflowgen -- A Modular ASIC/FPGA Flow Generator
An Emacs framework for the stubborn martian hacker
End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
A pre-RTL, power-performance model for fixed-function accelerators
A technical report on convolution arithmetic in the context of deep learning
AlexeyAB / darknet
Forked from pjreddie/darknetYOLOv4 / Scaled-YOLOv4 / YOLO - Neural Networks for Object Detection (Windows and Linux version of Darknet )
This repo includes ChatGPT prompt curation to use ChatGPT better.
🌙 LunarVim is an IDE layer for Neovim. Completely free and community driven.