ESnet SmartNIC hardware design repository.

AMD Xilinx University Program Vivado tutorial

AMD OpenNIC Project Overview

Introductory examples for using PYNQ with Alveo

This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multiple Alveo cards.

Vitis In-Depth Tutorials

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

Xilinx QDMA IP Drivers

NetFPGA 1G infrastructure and gateware

NetFPGA public repository

Verilog Content Addressable Memory Module

TCAM (Ternary Content-Addressable Memory) in Verilog

Yilong's NetFPGA-10G Repo

Open source FPGA-based NIC and platform for in-network compute

Verilog Ethernet components for FPGA implementation

native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches

It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.

萨塔妮娅 Project —— QQ机器人

Sata 2 Host Controller for FPGA implementation

mirror of https://git.elphel.com/Elphel/x393_sata

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Linux kernel source tree

Data Plane Development Kit

该资源为作者在CSDN的撰写Python图像处理文章的支撑，主要是Python实现图像处理、图像识别、图像分类等算法代码实现，希望该资源对您有所帮助，一起加油。

RDMA core userspace libraries and daemons

Support for HTTP in Scapy

JJQQKK上网助手

mirror of https://git.elphel.com/Elphel/eddr3

Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for setting up the interfaces and writing tasks for various oper…