Bouncy Castle Java Distribution (Mirror)

Configurable AES-GCM IP (128, 192, 256 bits)

Direct Access Memory for MPSoC

General Purpose AXI Direct Memory Access

AXI4-based Direct Memory Access (DMA) controller

A Direct Memory Access Controller (DMAC) with AHB-lite bus interface

automatic-verilog based on vimscript

基于Miracl的国密算法SM9实现

ECDH and ECDSA for 8-bit, 32-bit, and 64-bit processors.

Make your first side-channel attack on public datasets with eShard. This is a mirror of scared Gitlab repository. All contributions and merge request must be done through Gitlab project.

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Galois Couter Mode implementation in Verilog.

Flexible I/O Tester

This is a project in which side-channel attacks are researched and developed.

IC design and development should be faster，simpler and more reliable

AXI Mini Direct Memory Access (verilog)

Python SM4

A very small ECC implementation for 8-bit microcontrollers