opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A CPU implemented in a modular synthesizer

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

CPU Design Based on RISCV ISA

tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

EE577b-Course-Project

Chisel implementation of Neural Processing Unit for System on the Chip

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

8-bit RISC Processor on Logisim

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.

SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU

Domain Specific Hardware Accelerators - VLSI CAD Project

NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs

An 8-bit processor in VHDL based on a simple instruction set

RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

A simple processor designed using Verilog and Altera DE1 development board.

EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and imp…