Must-have verilog systemverilog modules
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Updated
Nov 7, 2024 - Verilog
Must-have verilog systemverilog modules
Simple UART controller for FPGA written in VHDL
Library code for upcoming RetroClash book
Altera wrappers for C applications using Altera's 16550 UART Core through Avalon Bus on Cyclone V.
Driver - Library for C applications using Altera's UART Core through Avalon Bus on Cyclone V.
The project is a C program that facilitates communication between two serial ports (COM ports). It creates two threads to handle the communication independently. The program reads packets from one serial port, verifies their integrity, and sends them to a system message queue.
ESP32-iUART (WROOM-32)
An ASCII twist on the classic Atari game, made entirely in ARM assembly language!
Hands-on Laboratory exercises on 8085 and AVR boards for "Microprocessors Laboratory" course in NTUA
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