wishbone

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Here are 52 public repositories matching this topic...

ZipCPU / zipcpu

Star

A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

Updated Nov 30, 2024
Verilog

ZipCPU / wb2axip

Star

Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus

Updated Jan 12, 2024
Verilog

ZipCPU / wbuart32

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A simple, basic, formally verified UART controller

fpga verilog uart serialport uart-verilog wishbone verilator wishbone-bus

Updated Jan 29, 2024
Verilog

ZipCPU / sdspi

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SD-Card controller, using either SPI, SDIO, or eMMC interfaces

spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface

Updated Nov 27, 2024
Verilog

ZipCPU / autofpga

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A utility for Composing FPGA designs from Peripherals

c-plus-plus fpga verilog wishbone verilator wishbone-bus

Updated Jan 18, 2024
C++

ZipCPU / openarty

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An Open Source configuration of the Arty platform

fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus

Updated Jan 17, 2024
Verilog

jakubcabal / uart-for-fpga

Sponsor

Star

Simple UART controller for FPGA written in VHDL

fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback

Updated Aug 7, 2021
VHDL

ZipCPU / wbscope

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A wishbone controlled scope for FPGA's

fpga verilog debugging-tools wishbone verilator wishbone-bus

Updated Jan 12, 2024
Verilog

lxp32 / lxp32-cpu

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A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

cpu fpga assembly vhdl assembler risc wishbone soft-core risc-processor wishbone-bus risc-cpu

Updated Dec 3, 2024
Assembly

ZipCPU / dbgbus

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A collection of debugging busses developed and presented at zipcpu.com

verilog debugging-tools wishbone fgpa verilator wishbone-bus

Updated Jan 18, 2024
Verilog

ZipCPU / s6soc

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CMod-S6 SoC

fpga fpga-soc wishbone verilator zipcpu wishbone-bus

Updated Jan 6, 2018
Verilog

stnolting / wb_spi_bridge

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🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

flash fpga memory vhdl spi wishbone xip neorv32

Updated Nov 29, 2021
VHDL

ZipCPU / wbfmtx

Star

A wishbone controlled FM transmitter hack

fpga hack verilog wishbone verilog-components wishbone-bus fm-transmitter

Updated Jan 16, 2024
Verilog

BLangOS / VexRiscV_with_HW-GDB_Server

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VexRiscV system with GDB-Server in Hardware

microcontroller vhdl fpga-soc risc-v c-language wishbone rsp gdbserver vexriscv

Updated Jul 5, 2023
VHDL

lingbai-kong / computer-system

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同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植

cpu gpio fpga uart sdcard big-endian wishbone ucosii sopc tongji-university ddr2 dynamic-pipelines openmips

Updated Jun 3, 2023
Verilog

pbing / ibex_wb

Star

RISC-V Ibex core with Wishbone B4 interface

riscv systemverilog risc-v wishbone wishbone-bus

Updated Dec 24, 2019
HTML

hotwolf / WbXbc

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HDL components to build a customized Wishbone crossbar switch

verilog hdl wishbone crossbar

Updated May 30, 2019
SystemVerilog

merledu / caravan

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A caravan equipped with API for creating bus protocols in Chisel with ease.

chisel3 wishbone caravan amba chisel-generator on-chip-network bus-protocols

Updated Nov 20, 2024
Scala

PacoReinaCampo / MPSoC-DMA

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Direct Access Memory for MPSoC

wishbone ahb3-lite

Updated Oct 30, 2024
SystemVerilog

rschlaikjer / fpga-3-softcores

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Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware

fpga risc-v wishbone softcore

Updated Aug 24, 2020
Verilog

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wishbone

Here are 52 public repositories matching this topic...

ZipCPU / zipcpu

ZipCPU / wb2axip

ZipCPU / wbuart32

ZipCPU / sdspi

ZipCPU / autofpga

ZipCPU / openarty

jakubcabal / uart-for-fpga

ZipCPU / wbscope

lxp32 / lxp32-cpu

ZipCPU / dbgbus

ZipCPU / s6soc

stnolting / wb_spi_bridge

ZipCPU / wbfmtx

BLangOS / VexRiscV_with_HW-GDB_Server

lingbai-kong / computer-system

pbing / ibex_wb

hotwolf / WbXbc

merledu / caravan

PacoReinaCampo / MPSoC-DMA

rschlaikjer / fpga-3-softcores

Improve this page

Add this topic to your repo