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Commits on Oct 31, 2016

• [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.

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  atamazov

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• [Hexagon] Don't expand mux instructions with both sources identical

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  Krzysztof Parzyszek

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• [SystemZ] Rework processor feature definitions and add -mcpu=archX support

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  uweigand

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• [SystemZ] Guard LEFR/LFER with FeatureVector

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  uweigand

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• [SystemZ] Correctly diagnose missing features in AsmParser

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  uweigand

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• [SystemZ] Fix encoding of MVCK and .insn ss

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  uweigand

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• Second attempt at r285517.

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  dnuzman

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• [SystemZ] Model 2 VBU units (not 1) in SystemZScheduleZ13.td.

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  JonPsson

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• Improved cost model for FDIV and FSQRT, by Andrew Tischenko

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  alexey-bataev

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• [AVX-512] Add missing patterns for selecting masked vector extracts that started from shuffles.

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  topperc

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• [SCEV] Try to order n-ary expressions in CompareValueComplexity

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  sanjoy

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Commits on Oct 30, 2016

• [SCEV] In CompareValueComplexity, order global values by their name

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  sanjoy

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• [SCEV] Use auto for consistency with an upcoming change; NFC

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  sanjoy

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• [DAG] x | x --> x

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  rotateright

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• [DAG] x & x --> x

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  rotateright

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• Revert r285517 due to build failures.

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  dnuzman

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• [LoopVectorize] Make interleaved-accesses analysis less conservative about

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  dnuzman

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• [X86] Use intrinsics table for PMADDUBSW and PMADDWD so that we can use the legacy intrinsics to select EVEX encoded instructions when available.

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  topperc

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• [ThinLTO] Use per-summary flag to prevent exporting locals used in inline asm

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  teresajohnson

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• [ThinLTO] Correctly resolve linkonce when importing aliasee

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  teresajohnson

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• [X86] Don't use loadv2i64 on SSE version of PMULHRSW. Use memopv2i64 instead.

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  topperc

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Commits on Oct 29, 2016

• NativeFormatting.cpp: Fix build for mingw. Where would writePadding() be?

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  chapuni

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• [ThinLTO] Rename doPromoteLocalToGlobal to shouldPromoteLocalToGlobal (NFC)

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  teresajohnson

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• [ThinLTO] Use NoPromote flag in summary during promotion

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  teresajohnson

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• IR: Remove a no longer needed assert.

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  pcc

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• [X86] Use intrinsics table for VPMULHRSW intrincis so that the legacy intrinsics can select EVEX encoded instructions when available.

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  topperc

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• [ValueTracking] recognize more variants of smin/smax

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  rotateright

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• [InstCombine] re-use bitcasted compare operands in selects (PR28001)

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  rotateright

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• [DAGCombiner] (REAPPLIED) Add vector demanded elements support to computeKnownBits

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  RKSimon

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• Fixed FMA + FNEG combine.

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  Elena Demikhovsky

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• AMDGPU: Use 1/2pi inline imm on VI

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  arsenm

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• AArch64DeadRegisterDefinitionsPass: Cleanup; NFC

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  MatzeB

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• Define calculateDbgStreamSize for consistency.

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  rui314

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• [APFloat] Remove the redundent function body of uninitialized ctor, which should be done in r285468

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  timshen91

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• Resubmit "Add support for advanced number formatting."

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  Zachary Turner

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