Asymmetrical FIFO with dynamic width

A Parameterizable Floating Point Unit (Verilog)

Bitonic sorter (Batcher's sorting network) written in Verilog.

Dynamically configurable CRC (Verilog)

Parameterizable Adders (Verilog)

Verilog Ethernet Switch (layer 2)

TCAM (Ternary Content-Addressable Memory) in Verilog

Cyclic code over GF(2) - Verilog

Polynomial arithmetic (Verilog)

Hamming code implementation in Verilog

Hash Table on Verilog (Suspended)

Verilog 8b10b encoder/decoder

Dynamic VGA Controller (Suspended)

AXI-Stream USB 2.0 HS Device Bridge (Verilog)

DSP in FPGA

FPGA basic digital devices

Milandr Evaluation Kits

AXI Stream UART (verilog)

Real-Valued Sequences DFT algorithms

AXI Mini Direct Memory Access (verilog)

Zynq-7000 MCS Creator

Signal-to-Noise Calculation (written in Matlab scripting language)